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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:07 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:17 +0200 |
| commit | 9260319e7411ff8281700a532caa436f40120ec4 (patch) | |
| tree | 2f6bfe5f3458dd49d328d3a9eb508595450adec0 /gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259 | |
| parent | 225caa38269323af1bfc2daadff5ec8bd930747f (diff) | |
| download | qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.tar.gz qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.zip | |
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Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259 | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259 b/gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259 new file mode 100644 index 000000000..fbc5dc5c0 --- /dev/null +++ b/gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259 @@ -0,0 +1,14 @@ +The cause code of a trap changes when qemu is nested in another qemu +Description of problem: +I am studying the feasibility of doing some practical work on RISCV plates. Since I don't have these boards yet, I'm emulating it with qemu. The practice in turn consists of launching with qemu a very small operating system with two tasks that make a series of system calls. + +When I run this practice on my host it works correctly, but when I run it on an Ubuntu emulated in riscv with qemu, the cause code for the trap changes (the first bit of the code). + +The demo can be found in this repository: https://github.com/Sft570/qemu-bug-report +Steps to reproduce: +1. Clone the repository on the host and run the demo with "make qemu" +2. Emulate with qemu ubuntu in riscv, clone the repository and run the demo with "make qemu". + +The error displayed shows the change of the cause code bit. You can analyze its behavior in the trap.c file in the src folder. +Additional information: + |