clean up repository

1 files changed, 0 insertions, 17 deletions

diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/1649 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/1649
deleted file mode 100644
index 67d58bf47..000000000
--- a/gitlab/issues_text/target_riscv/host_missing/accel_missing/1649
+++ /dev/null
@@ -1,17 +0,0 @@
-"slli" instruction before "la" and "csrw" sequence leads to failure in setting the cs register
-Description of problem:
-slli a0, a0, 8 (1)
-    la a0, mtimvec (2)
-    csrw mtvec, a0 (3)
-    mtimvec:       (4)
-
-For the above assembly snippet, the mtvec could be successfully set to the value of a0 
-without the presence of the line (1) or with the shift amount being zero. However, 
-the mtvec can never be set successfully with the presence of line (1).
-Steps to reproduce:
-1. Create a test.s file and put these 4 lines of assembly into the file
-2. In terminal, run: "riscv64-unknown-elf-gcc -Ttext 0x80000000 -c test.s -o test", "riscv64-unknown-elf-objcopy test -S -O binary test", and "qemu-system-riscv64 test -s -S"
-3. In another terminal window, run [riscv64-unknown-elf-gdb -ex "target remote localhost:1234" -ex "layout asm"]. Keep running si command in gdb until you are at 0x80000000 where you shall see the first instruction as shown in line (1). Then keep going till you have stepped over the instruction shown in line (3). Now, run "p $mtvec" in gdb, you shall see its value being 0.
-4. Redo the above steps without line (1), you shall see mtvec loaded successfully with the correct value.
-Additional information:
-