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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
| commit | 3e4c5a6261770bced301b5e74233e7866166ea5b (patch) | |
| tree | 9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_riscv/host_missing/accel_missing/2463 | |
| parent | e5634e2806195bee44407853c4bf8776f7abfa4f (diff) | |
| download | qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.tar.gz qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.zip | |
clean up repository
Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_missing/2463')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_missing/2463 | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2463 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/2463 deleted file mode 100644 index f00ca2d5f..000000000 --- a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2463 +++ /dev/null @@ -1,9 +0,0 @@ -allow sifive_e to use more RAM -Description of problem: -For users like me that are still learning RISC bare-metal assembly, searching online you will find many tutorials and examples using sifive_e with Qemu, so it is the easy way to get started. - -I quickly ran into crashes with my tests because I did not realize that sifive_e is limited to 16K of RAM. -I realize the 16K limit is hard coded so that it matches the real hardware, but that makes it very hard to run a variety of tests. -Additional information: -My fork of Qemu changes sifive_e to allow 256MB. -https://github.com/panjea/qemu/commit/97cb89d778ebe3407a969b8282e2e7adb4be2971 |