add new classifier result

1 files changed, 149 insertions, 0 deletions

diff --git a/results/classifier/105/semantic/1923197 b/results/classifier/105/semantic/1923197
new file mode 100644
index 000000000..06e794798
--- /dev/null
+++ b/results/classifier/105/semantic/1923197
@@ -0,0 +1,149 @@
+semantic: 0.907
+mistranslation: 0.879
+other: 0.869
+assembly: 0.855
+instruction: 0.854
+socket: 0.832
+device: 0.813
+graphic: 0.805
+KVM: 0.794
+vnc: 0.737
+boot: 0.724
+network: 0.710
+
+RISC-V priviledged instruction error
+
+Hello when performing an MRET with MPP set to something else than 0b11 in MSTATUS, 'Invalid Instruction' exception will be triggered. The problem appeared in code after version 5.2.0.
+
+<pre>
+  # setup interrupt handling for monitor mode
+  la t0, entry_loop
+  la t1, entry_trap
+  li t2, 0x888
+  li t3, 0x1880 # MPP in MSTATUS selects to which mode to return & MPIE selects if to enable interrupts after MRET
+  csrw mepc, t0
+  csrw mtvec, t1
+  csrs mie, t2
+  csrs mstatus, t3
+
+  # if supervisor mode not supported, then loop forever
+  csrr t0, misa
+  li t1, 0x40000
+  and t2, t1, t0
+  beqz t2, 1f
+
+  # setup interrupt i& exception delegation for supervisor mode
+  li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
+  li t1, 0x1000
+  #li t2, 0x300 # bit 8 & 9 is for ecall from user & supervisor mode
+  #li t3, 0x222
+  csrw mepc, t0
+  csrc mstatus, t1
+  #csrs medeleg, t2
+  #csrs mideleg, t3
+
+  # pass mhartid as first parameter to supervisor
+  csrr a0, mhartid
+
+1:
+  mret
+</pre>
+
+I'm guessing that this is a bug in your guest as it hasn't configured PMP regions.
+
+From the RISC-V spec:
+
+"
+If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an
+S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.
+"
+
+Confusingly implemented here means implemented in hardware, not just configured.
+
+You can check this by reverting this QEMU commit:
+
+commit d102f19a2085ac931cb998e6153b73248cca49f1
+Author: Atish Patra <email address hidden>
+Date:   Wed Dec 23 11:25:53 2020 -0800
+
+    target/riscv/pmp: Raise exception if no PMP entry is configured
+    
+    As per the privilege specification, any access from S/U mode should fail
+    if no pmp region is configured.
+    
+    Signed-off-by: Atish Patra <email address hidden>
+    Reviewed-by: Alistair Francis <email address hidden>
+    Message-id: <email address hidden>
+    Signed-off-by: Alistair Francis <email address hidden>
+
+
+Hello Francis,
+
+I'll configure PMP than do the test again. Sorry I hadn't understood what
+changed between version 5.2 and 6.0-rc2, since my code worked before.
+
+Best regards,
+Teodori Serge
+
+On Thu, 15 Apr 2021, 06:15 Alistair Francis, <email address hidden>
+wrote:
+
+> I'm guessing that this is a bug in your guest as it hasn't configured
+> PMP regions.
+>
+> >From the RISC-V spec:
+>
+> "
+> If no PMP entry matches an M-mode access, the access succeeds. If no PMP
+> entry matches an
+> S-mode or U-mode access, but at least one PMP entry is implemented, the
+> access fails.
+> "
+>
+> Confusingly implemented here means implemented in hardware, not just
+> configured.
+>
+> ** Changed in: qemu
+>        Status: Confirmed => Invalid
+>
+> --
+> You received this bug notification because you are subscribed to the bug
+> report.
+> https://bugs.launchpad.net/bugs/1923197
+>
+> Title:
+>   RISC-V priviledged instruction error
+>
+> To manage notifications about this bug go to:
+> https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
+>
+
+
+We fixed a bug to make QEMU act more like hardware, which now means that PMP must be configured in M-mode.
+
+Hello Francis,
+
+Yes thank you. I added code to setup a basic PMP and it works now. Thank
+you and best regards,
+
+Teodori Serge
+
+On Sun, 18 Apr 2021, 05:55 Alistair Francis, <email address hidden>
+wrote:
+
+> We fixed a bug to make QEMU act more like hardware, which now means that
+> PMP must be configured in M-mode.
+>
+> --
+> You received this bug notification because you are subscribed to the bug
+> report.
+> https://bugs.launchpad.net/bugs/1923197
+>
+> Title:
+>   RISC-V priviledged instruction error
+>
+> To manage notifications about this bug go to:
+> https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions
+>
+
+