add 18th iteration of classifier

1 files changed, 48 insertions, 0 deletions

diff --git a/results/classifier/118/none/2478 b/results/classifier/118/none/2478
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+graphic: 0.699
+arm: 0.672
+kernel: 0.639
+device: 0.639
+architecture: 0.612
+register: 0.530
+performance: 0.509
+semantic: 0.473
+vnc: 0.389
+peripherals: 0.380
+debug: 0.337
+assembly: 0.335
+ppc: 0.324
+TCG: 0.279
+PID: 0.277
+network: 0.260
+hypervisor: 0.248
+files: 0.248
+socket: 0.232
+VMM: 0.225
+user-level: 0.216
+x86: 0.208
+virtual: 0.205
+permissions: 0.170
+risc-v: 0.167
+boot: 0.132
+i386: 0.101
+mistranslation: 0.095
+KVM: 0.048
+
+STM32F1 STM32VLDicovery board: incorrect clock register setting
+Description of problem:
+The execution of the program hangs when testing, from libopencm3 clock initialization, the status of the clock in ``rcc_wait_for_osc_ready()``. This function https://github.com/libopencm3/libopencm3/blob/master/lib/stm32/f1/rcc.c#L366 loops until the bit stating that the oscillator is stabilized is set. I am unable to find in qemu this bit being set upon clock initialization, which I believe is an hardware emulation shortcoming. Commenting this line in libopencm3 allows for the emulation to complete correctly, but I believe the error lies in the hardware emulation and not in the libopencm3 test. Reading the status of ``RCC_CR`` from ``gdb-multiarch`` probing the QEMU internal state returns 0, leading to the failure of the test at https://github.com/libopencm3/libopencm3/blob/master/lib/stm32/f1/rcc.c#L353
+
+See https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf for the expected behavior of this register content on page 99/1136
+```
+7.3.1 Clock control register (RCC_CR)
+
+Bit 17 HSERDY: External high-speed clock ready flag
+Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
+HSE oscillator clock to fall down after HSEON reset.
+0: HSE oscillator not ready
+1: HSE oscillator ready
+```
+Steps to reproduce:
+1. git clone --recursive https://github.com/libopencm3/libopencm3-examples
+2. make
+3. qemu-system-arm -M stm32vldiscovery -nographic -serial mon:stdio -kernel examples/stm32/f1/stm32vl-discovery/usart/usart.elf