add 18th iteration of classifier

1 files changed, 87 insertions, 0 deletions

diff --git a/results/classifier/118/review/1458 b/results/classifier/118/review/1458
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index 000000000..eeb1e3c2b
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+++ b/results/classifier/118/review/1458
@@ -0,0 +1,87 @@
+architecture: 0.881
+x86: 0.784
+device: 0.779
+graphic: 0.761
+VMM: 0.636
+register: 0.629
+TCG: 0.564
+network: 0.487
+vnc: 0.469
+socket: 0.446
+performance: 0.434
+permissions: 0.434
+ppc: 0.423
+PID: 0.369
+semantic: 0.366
+debug: 0.355
+kernel: 0.354
+arm: 0.353
+hypervisor: 0.323
+boot: 0.318
+mistranslation: 0.304
+peripherals: 0.288
+user-level: 0.243
+virtual: 0.231
+files: 0.228
+i386: 0.225
+assembly: 0.210
+risc-v: 0.201
+KVM: 0.187
+--------------------
+register: 0.841
+virtual: 0.632
+debug: 0.456
+TCG: 0.210
+architecture: 0.203
+hypervisor: 0.200
+device: 0.117
+semantic: 0.075
+x86: 0.072
+VMM: 0.029
+files: 0.019
+PID: 0.018
+kernel: 0.016
+assembly: 0.009
+peripherals: 0.009
+risc-v: 0.008
+user-level: 0.008
+socket: 0.008
+performance: 0.006
+ppc: 0.004
+boot: 0.003
+vnc: 0.003
+KVM: 0.003
+network: 0.003
+arm: 0.002
+i386: 0.002
+permissions: 0.002
+graphic: 0.001
+mistranslation: 0.001
+
+ns16550a reg-shift incorrect for qemu-system-riscv64
+Description of problem:
+Missing reg-shift 0 on the ns16550n in qemu-system-riscv64 creates an impossible assumption case.
+Steps to reproduce:
+1. qemu-system-riscv64 -M virt,dumpdtb=dtb
+2. dtc dtb | less
+
+                serial@10000000 {
+                        interrupts = <0x0a>;
+                        interrupt-parent = <0x03>;
+                        clock-frequency = "\08@";
+                        reg = <0x00 0x10000000 0x00 0x100>;
+                        compatible = "ns16550a";
+                };
+
+Generally, ns16550a has a default reg-shift of 0 on x86,x86_64 for compatibility reasons.  All other architectures have an assumed reg-shift of 2 (or having the reg-shift assumption overridden by fdt providing a reg-shift property)
+
+Beyond the above, anything non-standard is assumed to be specified by the "reg-shift" property fdt.
+
+qemu-system-riscv64 seems to "assume" a reg-shift of 0.  Other riscv64 devices don't supply "reg-shift" (SiFive Unmatched) and "assume" 2.
+The above means driver writers don't actually know what to "assume" on riscv64 ns16550a when no reg-shift is present.
+
+
+Essentially, qemu-system-riscv64 needs to do one of the following:
+
+* If serial ns16550a with a uart reg-shift of 0 is intentional, qemu needs to advertise the deviance via "reg-shift 0"
+* If serial ns16550a with a uart reg-shift of 0 is unintentional, it needs updated to 2 so drivers can assume 2 on riscv64.