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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 16:27:09 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 16:27:09 +0000 |
| commit | 4d9e26c0333abd39bdbd039dcdb30ed429c475ba (patch) | |
| tree | 4010d5fb3e8bc48c110a2c1ff2a16b8648cb86bb /results/classifier/accel-gemma3:12b/kvm/424450 | |
| parent | 5541099586dbd6018574cb44e1934907c121526f (diff) | |
| download | qemu-analysis-4d9e26c0333abd39bdbd039dcdb30ed429c475ba.tar.gz qemu-analysis-4d9e26c0333abd39bdbd039dcdb30ed429c475ba.zip | |
add gemma accelerator classification results
Diffstat (limited to 'results/classifier/accel-gemma3:12b/kvm/424450')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/kvm/424450 | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/kvm/424450 b/results/classifier/accel-gemma3:12b/kvm/424450 new file mode 100644 index 000000000..4b650fe92 --- /dev/null +++ b/results/classifier/accel-gemma3:12b/kvm/424450 @@ -0,0 +1,15 @@ + +FDC reset should reset the MSR + +I believe that the MSR resgister should also be reset to zero on a software reset. All of the FDC hardware I have does this. +The current code leaves the MSR as 0x80, which means that the controller is ready for a write. The controller should not +be ready for a write while in reset. + +fdc.c Line 899 + /* Reset */ + if (!(value & FD_DOR_nRESET)) { + + fdctrl->msr = 0x00; + if (fdctrl->dor & FD_DOR_nRESET) { + FLOPPY_DPRINTF("controller enter RESET state\n"); + } + } else { \ No newline at end of file |