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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
| commit | d0c85e36e4de67af628d54e9ab577cc3fad7796a (patch) | |
| tree | f8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/gemma3:12b/hypervisor/1843254 | |
| parent | 7f4364274750eb8cb39a3e7493132fca1c01232e (diff) | |
| download | qemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz qemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip | |
add deepseek and gemma results
Diffstat (limited to 'results/classifier/gemma3:12b/hypervisor/1843254')
| -rw-r--r-- | results/classifier/gemma3:12b/hypervisor/1843254 | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/hypervisor/1843254 b/results/classifier/gemma3:12b/hypervisor/1843254 new file mode 100644 index 000000000..2fac22adb --- /dev/null +++ b/results/classifier/gemma3:12b/hypervisor/1843254 @@ -0,0 +1,4 @@ + +arm emulation of HCR.TID3 traps are not implemented + +On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3, which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers. However, setting that HCR bit has no effect and accesses to those ID registers are not trapped to EL2 with an EC syndrome value of 0x18. \ No newline at end of file |