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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
| commit | d0c85e36e4de67af628d54e9ab577cc3fad7796a (patch) | |
| tree | f8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/gemma3:12b/kernel/2511 | |
| parent | 7f4364274750eb8cb39a3e7493132fca1c01232e (diff) | |
| download | qemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz qemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip | |
add deepseek and gemma results
Diffstat (limited to 'results/classifier/gemma3:12b/kernel/2511')
| -rw-r--r-- | results/classifier/gemma3:12b/kernel/2511 | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/kernel/2511 b/results/classifier/gemma3:12b/kernel/2511 new file mode 100644 index 000000000..bcb8aba40 --- /dev/null +++ b/results/classifier/gemma3:12b/kernel/2511 @@ -0,0 +1,33 @@ + +Regression 9.1.0rc2: target/i386/tcg/access.c:18: access_prepare_mmu: Assertion '...' failed. +Description of problem: +Executing QEMU command line crashes with + ``` +qemu-system-x86_64: ../target/i386/tcg/access.c:18: access_prepare_mmu: Assertion `size > 0 && size <= TARGET_PAGE_SIZE' failed. + ``` +Steps to reproduce: +1. Download https://www.qemu-advent-calendar.org/2020/download/day07.tar.gz +2. Execute with QEMU command line +Additional information: +git bisect finishes with: + ``` +8b131065080af3cf2dda04e4e190c5a74fec2f31 is the first bad commit +commit 8b131065080af3cf2dda04e4e190c5a74fec2f31 +Author: Paolo Bonzini <pbonzini@redhat.com> +Date: Tue Jun 18 09:13:49 2024 +0200 + + target/i386/tcg: use X86Access for TSS access + + This takes care of probing the vaddr range in advance, and is also faster + because it avoids repeated TLB lookups. It also matches the Intel manual + better, as it says "Checks that the current (old) TSS, new TSS, and all + segment descriptors used in the task switch are paged into system memory"; + note however that it's not clear how the processor checks for segment + descriptors, and this check is not included in the AMD manual. + + Reviewed-by: Richard Henderson <richard.henderson@linaro.org> + Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> + + target/i386/tcg/seg_helper.c | 110 +++++++++++++++++++++++-------------------- + 1 file changed, 58 insertions(+), 52 deletions(-) + ``` |