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authorChristian Krinitsin <mail@krinitsin.com>2025-07-03 07:27:52 +0000
committerChristian Krinitsin <mail@krinitsin.com>2025-07-03 07:27:52 +0000
commitd0c85e36e4de67af628d54e9ab577cc3fad7796a (patch)
treef8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/gemma3:12b/peripherals/2550
parent7f4364274750eb8cb39a3e7493132fca1c01232e (diff)
downloadqemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz
qemu-analysis-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip
add deepseek and gemma results
Diffstat (limited to 'results/classifier/gemma3:12b/peripherals/2550')
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diff --git a/results/classifier/gemma3:12b/peripherals/2550 b/results/classifier/gemma3:12b/peripherals/2550
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+
+GICv3 vGIC system registers not initialized on ARM Cortex-A15
+Description of problem:
+For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc
+Steps to reproduce:
+The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward.
+Additional information:
+Suggested fix:
+```diff
+index 20c2737f17..136b513bda 100644
+--- a/target/arm/tcg/cpu32.c
++++ b/target/arm/tcg/cpu32.c
+@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj)
+     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+     cpu->isar.reset_pmcr_el0 = 0x410F3000;
++
++    /* From B3.5 VGIC Type register */
++    cpu->gic_num_lrs = 4;
++    cpu->gic_vpribits = 5;
++    cpu->gic_vprebits = 5;
++
+     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
+ }
+
+```