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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-06 16:43:19 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-06 16:43:19 +0000 |
| commit | 238ec2b7cc1557d6f34c33cc482e4d0cd3e266dd (patch) | |
| tree | cd8a1b75ba7b3543eb7fe6857f408e7be4d9fd0b /results/classifier/gemma3:27b/instruction/1862167 | |
| parent | 96049c939b1916d80532630d63c14e04d5244f1d (diff) | |
| download | qemu-analysis-238ec2b7cc1557d6f34c33cc482e4d0cd3e266dd.tar.gz qemu-analysis-238ec2b7cc1557d6f34c33cc482e4d0cd3e266dd.zip | |
add results
Diffstat (limited to 'results/classifier/gemma3:27b/instruction/1862167')
| -rw-r--r-- | results/classifier/gemma3:27b/instruction/1862167 | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/results/classifier/gemma3:27b/instruction/1862167 b/results/classifier/gemma3:27b/instruction/1862167 new file mode 100644 index 000000000..512a54b7c --- /dev/null +++ b/results/classifier/gemma3:27b/instruction/1862167 @@ -0,0 +1,6 @@ + + + +Variation of SVE register size (qemu-user-aarch64) + +Specification of ARMv8-A SVE extention allows various values for the size of the SVE register. On the other hand, it seems that the current qemu-aarch64 supports only the maximum length of 2048 bits as the SVE register size. I am writing an assembler program for a CPU that is compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when this is run with qemu-user-aarch64, a 2048-bit load / store instruction is executed This causes a segmentation fault. Shouldn't qeum-user-aarch64 have an option to specify the SVE register size? \ No newline at end of file |