filter for semantic-user-mode bugs

1 files changed, 33 insertions, 0 deletions

diff --git a/results/classifier/semantic-bugs-usermode/test/1863247 b/results/classifier/semantic-bugs-usermode/test/1863247
new file mode 100644
index 000000000..072da78e3
--- /dev/null
+++ b/results/classifier/semantic-bugs-usermode/test/1863247
@@ -0,0 +1,33 @@
+instruction: 0.742
+device: 0.668
+graphic: 0.540
+semantic: 0.501
+other: 0.498
+mistranslation: 0.393
+socket: 0.384
+network: 0.383
+vnc: 0.341
+boot: 0.254
+assembly: 0.250
+KVM: 0.178
+
+AArch64 EXT instruction for V register does not clear MSB side bits
+
+On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value.
+
+Example
+ext v0.16b, v1.16b v2.16b, 8
+
+After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width.
+
+Yep.
+
+Fixed here:
+https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b
+
+
+Thank you for bug fix.
+I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug.
+
+All of those, and tbl, tbx, ins, are fixed in the three subsequent commits.
+