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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-05 20:00:38 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-05 20:00:38 +0200 |
| commit | 96049c939b1916d80532630d63c14e04d5244f1d (patch) | |
| tree | 7fb9df428f074078e714f1e038210cdff887185a /results/classifier/semantic-bugs/1863247 | |
| parent | 40bbb77d4dfebff4f99c2f90b2c0db737b0ecc5a (diff) | |
| download | qemu-analysis-96049c939b1916d80532630d63c14e04d5244f1d.tar.gz qemu-analysis-96049c939b1916d80532630d63c14e04d5244f1d.zip | |
lock user-mode and semantic-bugs
Diffstat (limited to 'results/classifier/semantic-bugs/1863247')
| -rw-r--r-- | results/classifier/semantic-bugs/1863247 | 27 |
1 files changed, 2 insertions, 25 deletions
diff --git a/results/classifier/semantic-bugs/1863247 b/results/classifier/semantic-bugs/1863247 index 072da78e3..752dcb305 100644 --- a/results/classifier/semantic-bugs/1863247 +++ b/results/classifier/semantic-bugs/1863247 @@ -1,15 +1,4 @@ -instruction: 0.742 -device: 0.668 -graphic: 0.540 -semantic: 0.501 -other: 0.498 -mistranslation: 0.393 -socket: 0.384 -network: 0.383 -vnc: 0.341 -boot: 0.254 -assembly: 0.250 -KVM: 0.178 + AArch64 EXT instruction for V register does not clear MSB side bits @@ -18,16 +7,4 @@ On AArch64 CPU with SVE register, there seems to be a bug in the operation when Example ext v0.16b, v1.16b v2.16b, 8 -After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. - -Yep. - -Fixed here: -https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b - - -Thank you for bug fix. -I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug. - -All of those, and tbl, tbx, ins, are fixed in the three subsequent commits. - +After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. \ No newline at end of file |