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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-16 14:55:48 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-16 14:55:48 +0200 |
| commit | 63d2e9d409831aa8582787234cae4741847504b7 (patch) | |
| tree | 595fae753d2eb293437226eaab2eed208463f132 /results/scraper/box64/595 | |
| parent | 2843bb65aeaeb86eb89bf3d9690db61b9dc6306e (diff) | |
| download | qemu-analysis-box64.tar.gz qemu-analysis-box64.zip | |
add box64 bug reports box64
Diffstat (limited to 'results/scraper/box64/595')
| -rw-r--r-- | results/scraper/box64/595 | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/results/scraper/box64/595 b/results/scraper/box64/595 new file mode 100644 index 000000000..8cc390f89 --- /dev/null +++ b/results/scraper/box64/595 @@ -0,0 +1,4 @@ +[RV64] JIT of vector instructions +RISC-V is still a young architecture that has more extensions to be added. Currently, the “V” vector extension is in a [frozen state](https://github.com/riscv/riscv-v-spec/tree/57998875a3aebfe53407e82f1ec9fda0fef746c7) and is expected to be ratified in the near future. T-Head has implemented a draft version (namely 0.7.1) of the V extension in their cores before, but apparently this is not widely adopted by most distros. + +As a result, we still lack real-world support for the (stable) vector extension as of now. This poses a challenge if we want to directly translate ARM neon instructions to their RISC-V V counterparts. Should we leave these instructions to the emulation interpreter or use scalar instructions as a workaround? \ No newline at end of file |