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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-17 09:10:43 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-17 09:10:43 +0200 |
| commit | f2ec263023649e596c5076df32c2d328bc9393d2 (patch) | |
| tree | 5dd86caab46e552bd2e62bf9c4fb1a7504a44db4 /results/scraper/fex/2780 | |
| parent | 63d2e9d409831aa8582787234cae4741847504b7 (diff) | |
| download | qemu-analysis-main.tar.gz qemu-analysis-main.zip | |
Diffstat (limited to 'results/scraper/fex/2780')
| -rw-r--r-- | results/scraper/fex/2780 | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/results/scraper/fex/2780 b/results/scraper/fex/2780 new file mode 100644 index 000000000..83b01995c --- /dev/null +++ b/results/scraper/fex/2780 @@ -0,0 +1,35 @@ +SRA inserts arbitrary move for some reason? +Simple unit test to see the issue. +```asm +%ifdef CONFIG +{ + "RegData": { + "RAX": "0x4" + } +} +%endif + +mov rax, 1 +mov rbx, 1 +shld rax, rbx, 2 + +hlt +``` + +Resulting IR for the shld instruction. +``` + (%3 i0) BeginBlock %2(Invalid) + %4(GPRFixed3) i64 = LoadRegister #0x0, #0x20, GPR, GPRFixed, u8:Tmp:Size + %5(GPR0) i64 = LoadRegister #0x0, #0x8, GPR, GPRFixed, u8:Tmp:Size + %6(GPRFixed0) i64 = Extr %5(GPR0) i64, %4(GPRFixed3) i64, #0x3e + ... +``` + +As seen, the first source to the `Extr` IR op doesn't get assigned to static register allocation for some reason. +This results in a redundant move when the Arm64 JIT emits code. +```asm +0x0000ffff840800a4 aa0403f4 mov x20, x4 +0x0000ffff840800a8 93c7fa84 extr x4, x20, x7, #62 +``` + +Unknown how many places in the JIT this causes arbitrary moves. Noticed while writing #2779 \ No newline at end of file |