diff options
| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-17 09:10:43 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-17 09:10:43 +0200 |
| commit | f2ec263023649e596c5076df32c2d328bc9393d2 (patch) | |
| tree | 5dd86caab46e552bd2e62bf9c4fb1a7504a44db4 /results/scraper/fex/761 | |
| parent | 63d2e9d409831aa8582787234cae4741847504b7 (diff) | |
| download | qemu-analysis-main.tar.gz qemu-analysis-main.zip | |
Diffstat (limited to 'results/scraper/fex/761')
| -rw-r--r-- | results/scraper/fex/761 | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/results/scraper/fex/761 b/results/scraper/fex/761 new file mode 100644 index 000000000..a1351f0ec --- /dev/null +++ b/results/scraper/fex/761 @@ -0,0 +1,10 @@ +Implement Intel style cross-cacheline atomics with ARM TME +We don't currently have a CPU architecture that supports TME but we should track this. +Any atomic operation that crosses a cacheline will fault on ARM. +We then need to do two CAS loops to implement this. +Problem is that this can tear. + +Intel works around this problem by supporting "Split locks" +AMD should also just tear in this situation. + +Once we have an architecture that supports TME, use it to hold ownership of both sides of the cacheline and do the ops to ensure no tearing. \ No newline at end of file |