diff options
Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_missing/1978')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_missing/1978 | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/1978 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/1978 new file mode 100644 index 000000000..1ff6d1ca2 --- /dev/null +++ b/gitlab/issues_text/target_riscv/host_missing/accel_missing/1978 @@ -0,0 +1,5 @@ +sifive_e : erroneous CLINT frequency +Description of problem: +CLINT's `mtime` updates at a clock frequency of [10 MHz](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/riscv/sifive_e.c?ref_type=heads#L228), whereas [SiFive documentation](https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf?_gl=1*w2ieef*_ga*MTcyNDI2MjM0Ny4xNjk2ODcwNTM3*_ga_T369JS7J9N*MTY5Njg3MDUzNy4xLjAuMTY5Njg3MDUzNy42MC4wLjA.) shows that its clock frequency is 32.768 kHz (i.e., the RTC clock). + +This difference leads to unexpected timing behavior. Due to the difference, it can even trigger multiple nested interrupts as the IRQ routine is not able to return before a new timer interrupt is triggered. |