diff options
Diffstat (limited to 'results/classifier/118/kernel/1164')
| -rw-r--r-- | results/classifier/118/kernel/1164 | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/results/classifier/118/kernel/1164 b/results/classifier/118/kernel/1164 new file mode 100644 index 000000000..50db469ce --- /dev/null +++ b/results/classifier/118/kernel/1164 @@ -0,0 +1,47 @@ +kernel: 0.939 +device: 0.836 +network: 0.835 +register: 0.817 +ppc: 0.772 +architecture: 0.763 +vnc: 0.746 +socket: 0.741 +arm: 0.729 +graphic: 0.684 +files: 0.675 +permissions: 0.601 +risc-v: 0.591 +semantic: 0.548 +PID: 0.546 +TCG: 0.527 +debug: 0.490 +mistranslation: 0.484 +performance: 0.481 +boot: 0.477 +x86: 0.473 +VMM: 0.402 +KVM: 0.379 +i386: 0.371 +peripherals: 0.367 +hypervisor: 0.334 +assembly: 0.278 +virtual: 0.243 +user-level: 0.153 + +q35: incorrect values for PCIEXBAR masks +Description of problem: +https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ + +In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) + +There are two small issues in PCIEXBAR address mask handling: +- wrong bit positions for address mask bits (see PCIEXBAR description + in Q35 datasheet) +- incorrect usage of 64ADR_MASK + +Due to this, attempting to write a valid PCIEXBAR address may cause it to +shift to another address, causing memory layout corruption where emulated +MMIO regions may overlap real (passed through) MMIO ranges. Fix this +by providing correct values. +Additional information: +Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ) |