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Diffstat (limited to 'results/classifier/118/review/1978')
| -rw-r--r-- | results/classifier/118/review/1978 | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/results/classifier/118/review/1978 b/results/classifier/118/review/1978 new file mode 100644 index 000000000..7482ef016 --- /dev/null +++ b/results/classifier/118/review/1978 @@ -0,0 +1,65 @@ +mistranslation: 0.874 +risc-v: 0.863 +device: 0.855 +performance: 0.841 +files: 0.818 +vnc: 0.809 +graphic: 0.778 +network: 0.694 +socket: 0.635 +register: 0.606 +kernel: 0.564 +semantic: 0.524 +debug: 0.465 +permissions: 0.447 +peripherals: 0.435 +ppc: 0.427 +i386: 0.409 +architecture: 0.396 +boot: 0.385 +hypervisor: 0.307 +TCG: 0.274 +arm: 0.258 +x86: 0.253 +VMM: 0.242 +user-level: 0.215 +virtual: 0.189 +KVM: 0.146 +PID: 0.138 +assembly: 0.108 +-------------------- +debug: 0.636 +kernel: 0.467 +assembly: 0.459 +hypervisor: 0.321 +files: 0.268 +device: 0.249 +x86: 0.238 +performance: 0.216 +register: 0.159 +i386: 0.140 +arm: 0.115 +virtual: 0.099 +peripherals: 0.089 +ppc: 0.077 +architecture: 0.052 +PID: 0.016 +boot: 0.015 +semantic: 0.014 +TCG: 0.013 +risc-v: 0.012 +network: 0.008 +VMM: 0.008 +user-level: 0.005 +socket: 0.005 +KVM: 0.003 +permissions: 0.003 +graphic: 0.003 +vnc: 0.002 +mistranslation: 0.002 + +sifive_e : erroneous CLINT frequency +Description of problem: +CLINT's `mtime` updates at a clock frequency of [10 MHz](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/riscv/sifive_e.c?ref_type=heads#L228), whereas [SiFive documentation](https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf?_gl=1*w2ieef*_ga*MTcyNDI2MjM0Ny4xNjk2ODcwNTM3*_ga_T369JS7J9N*MTY5Njg3MDUzNy4xLjAuMTY5Njg3MDUzNy42MC4wLjA.) shows that its clock frequency is 32.768 kHz (i.e., the RTC clock). + +This difference leads to unexpected timing behavior. Due to the difference, it can even trigger multiple nested interrupts as the IRQ routine is not able to return before a new timer interrupt is triggered. |