diff options
Diffstat (limited to 'results/classifier/accel-gemma3:12b/tcg/1851939')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/tcg/1851939 | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/tcg/1851939 b/results/classifier/accel-gemma3:12b/tcg/1851939 new file mode 100644 index 000000000..f5e29bc12 --- /dev/null +++ b/results/classifier/accel-gemma3:12b/tcg/1851939 @@ -0,0 +1,17 @@ + +RISC-V mstatus TSR bit not correctly implemented + +Hi, + +since qemu 4.1.0 the TSR bit in mstatus register is supported. But it does not allow for executing sret in m-mode. + +From the RISC-V specifications: +"When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction +exception. When TSR=0, this operation is permitted in S-mode." + +This means an exception should only be raised when executing in S-mode, but not in M-mode, hence you should change the condition in helper_sret (target/riscv/op_helper.c) from: + if (env->priv_ver >= PRIV_VERSION_1_10_0 && + get_field(env->mstatus, MSTATUS_TSR)) +to: + if (env->priv_ver >= PRIV_VERSION_1_10_0 && + get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) \ No newline at end of file |