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Diffstat (limited to 'results/classifier/accel-gemma3:12b/tcg/1909823')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/tcg/1909823 | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/tcg/1909823 b/results/classifier/accel-gemma3:12b/tcg/1909823 new file mode 100644 index 000000000..93d753b08 --- /dev/null +++ b/results/classifier/accel-gemma3:12b/tcg/1909823 @@ -0,0 +1,8 @@ + +RDPMC check on PCE is backwards + +At [this line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225) the check on CR4_PCE_MASK is backwards: it's raising an exception if the flag is set (and CPL != 0) rather than if the flag is clear. + +It's low priority at the moment because the instruction isn't implemented, so you get an illegal opcode exception when expecting a GPF, or vice versa, but it's a time bomb for if it is ever implemented. + +The Intel docs also indicate that CR0.PE influences the protection; I don't know if that's already reflected in env->hflags & HF_CPL_MASK. \ No newline at end of file |