diff options
Diffstat (limited to 'results/classifier/deepseek-2-tmp/output/other/2550')
| -rw-r--r-- | results/classifier/deepseek-2-tmp/output/other/2550 | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/results/classifier/deepseek-2-tmp/output/other/2550 b/results/classifier/deepseek-2-tmp/output/other/2550 new file mode 100644 index 000000000..e15506a01 --- /dev/null +++ b/results/classifier/deepseek-2-tmp/output/other/2550 @@ -0,0 +1,26 @@ + +GICv3 vGIC system registers not initialized on ARM Cortex-A15 +Description of problem: +For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc +Steps to reproduce: +The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward. +Additional information: +Suggested fix: +```diff +index 20c2737f17..136b513bda 100644 +--- a/target/arm/tcg/cpu32.c ++++ b/target/arm/tcg/cpu32.c +@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj) + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + cpu->isar.reset_pmcr_el0 = 0x410F3000; ++ ++ /* From B3.5 VGIC Type register */ ++ cpu->gic_num_lrs = 4; ++ cpu->gic_vpribits = 5; ++ cpu->gic_vprebits = 5; ++ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); + } + +``` |