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+x86: 0.995
+semantic: 0.974
+architecture: 0.868
+device: 0.758
+graphic: 0.700
+ppc: 0.665
+debug: 0.650
+performance: 0.552
+vnc: 0.544
+operating system: 0.543
+i386: 0.538
+assembly: 0.531
+boot: 0.465
+permissions: 0.443
+kernel: 0.427
+socket: 0.426
+network: 0.393
+PID: 0.358
+register: 0.341
+mistranslation: 0.299
+risc-v: 0.293
+files: 0.280
+TCG: 0.255
+arm: 0.252
+alpha: 0.217
+VMM: 0.216
+KVM: 0.192
+virtual: 0.176
+peripherals: 0.166
+user-level: 0.144
+hypervisor: 0.126
+
+x86 SSE/SSE2/SSE3 instruction semantic bugs with NaN
+
+Description of problem
+The result of SSE/SSE2/SSE3 instructions with NaN is different from the CPU. From Intel manual Volume 1 Appendix D.4.2.2, they defined the behavior of such instructions with NaN. But I think QEMU did not implement this semantic exactly because the byte result is different.
+
+Steps to reproduce
+
+Compile this code
+
+void main() {
+    asm("mov rax, 0x000000007fffffff; push rax; mov rax, 0x00000000ffffffff; push rax; movdqu XMM1, [rsp];");
+    asm("mov rax, 0x2e711de7aa46af1a; push rax; mov rax, 0x7fffffff7fffffff; push rax; movdqu XMM2, [rsp];");
+    asm("addsubps xmm1, xmm2");
+}
+
+Execute and compare the result with the CPU. This problem happens with other SSE/SSE2/SSE3 instructions specified in the manual, Volume 1 Appendix D.4.2.2.
+
+CPU xmm1[3] = 0xffffffff
+
+QEMU xmm1[3] = 0x7fffffff
+
+Additional information
+This bug is discovered by research conducted by KAIST SoftSec.