1 files changed, 31 insertions, 0 deletions
diff --git a/results/classifier/zero-shot/108/other/1062 b/results/classifier/zero-shot/108/other/1062
new file mode 100644
index 000000000..f8ac851f6
--- /dev/null
+++ b/results/classifier/zero-shot/108/other/1062
@@ -0,0 +1,31 @@
+graphic: 0.906
+device: 0.826
+performance: 0.728
+socket: 0.727
+network: 0.651
+semantic: 0.646
+permissions: 0.635
+vnc: 0.606
+other: 0.562
+PID: 0.559
+files: 0.517
+boot: 0.478
+debug: 0.476
+KVM: 0.082
+
+AArch64: SCR_EL3.RW behaves incorrectly for CPUs with no AArch32
+Description of problem:
+In the ARM DDI 0487G.a, D13-3572, the SCR_EL3.RW bit is defined as RAO/WI if both EL2 and EL1 don't support Aarch32. However, the function `scr_write` in `target/arm/helper.c` does not reflect this behavior, even though it checks for Aarch32 EL1 support.
+
+This would break this EL3 code, which should run on cpu reset to attempt to return to EL1:
+```asm
+mov x1, #((1<<0)|(1<<2)|(1<<6)|(1<<7)|(1<<8)|(1<<9)) ; EL1h, DAIF masked
+mov SPSR_EL3, x1
+adr x1, 1f
+msr ELR_EL3, x1
+eret
+1:
+; something something
+```
+Additional information:
+