1 files changed, 58 insertions, 0 deletions
diff --git a/results/classifier/zero-shot/108/other/1550503 b/results/classifier/zero-shot/108/other/1550503
new file mode 100644
index 000000000..fc6ec3906
--- /dev/null
+++ b/results/classifier/zero-shot/108/other/1550503
@@ -0,0 +1,58 @@
+device: 0.755
+socket: 0.731
+PID: 0.706
+files: 0.605
+semantic: 0.591
+vnc: 0.573
+graphic: 0.554
+performance: 0.525
+network: 0.525
+other: 0.482
+debug: 0.459
+boot: 0.457
+permissions: 0.434
+KVM: 0.238
+
+target-arm/helper.c:5493: bad test ?
+
+[qemu/target-arm/helper.c:5493]: (style) Expression '(X & 0x1f) != 0xf80f0000' is always true.
+
+Source code is
+
+        (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
+
+but
+
+./qemu/target-arm/cpu.h:#define CPSR_M (0x1fU)
+
+./qemu/target-arm/cpu.h:#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
+
+On 26 February 2016 at 20:07, dcb <email address hidden> wrote:
+> Public bug reported:
+>
+> [qemu/target-arm/helper.c:5493]: (style) Expression '(X & 0x1f) !=
+> 0xf80f0000' is always true.
+>
+> Source code is
+>
+>         (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
+>
+> but
+>
+> ./qemu/target-arm/cpu.h:#define CPSR_M (0x1fU)
+>
+> ./qemu/target-arm/cpu.h:#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
+
+Yeah, that's a bug. Should be ARM_CPU_MODE_USR, not CPSR_USER.
+
+thanks
+-- PMM
+
+
+Should be fixed by http://patchwork.ozlabs.org/patch/590051/
+
+
+Fix should be part of QEMU v2.6.0:
+http://git.qemu.org/?p=qemu.git;a=commit;h=8c4f0eb94cc65ee32a
+... so I think this ticket can now be closed.
+