diff options
Diffstat (limited to 'results/classifier/zero-shot/108/other/653')
| -rw-r--r-- | results/classifier/zero-shot/108/other/653 | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/results/classifier/zero-shot/108/other/653 b/results/classifier/zero-shot/108/other/653 new file mode 100644 index 000000000..b9837c813 --- /dev/null +++ b/results/classifier/zero-shot/108/other/653 @@ -0,0 +1,74 @@ +other: 0.777 +permissions: 0.719 +PID: 0.705 +device: 0.694 +performance: 0.694 +files: 0.688 +semantic: 0.679 +graphic: 0.679 +debug: 0.675 +socket: 0.612 +vnc: 0.610 +KVM: 0.589 +boot: 0.565 +network: 0.540 + +Tricore: wrong implementation of OPC2_32_RCRW_IMASK and OPC2_32_RCRW_INSERT in target/tricore/translate.c +Description of problem: +The translation of the instructions is not done properly. +please check +https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8 + +1) Implemented in target/tricore/translate.c as + switch (op2) { + case OPC2_32_RCRW_IMASK: + tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); + tcg_gen_movi_tl(temp2, (1 << width) - 1); + tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); + tcg_gen_movi_tl(temp2, const4); + tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); + break; + case OPC2_32_RCRW_INSERT: + temp3 = tcg_temp_new(); + + tcg_gen_movi_tl(temp, width); + tcg_gen_movi_tl(temp2, const4); + tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); + gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); + + tcg_temp_free(temp3); + break; + +2) Should be + case OPC2_32_RCRW_IMASK: + tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); + tcg_gen_movi_tl(temp2, (1 << width) - 1); + tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); + tcg_gen_movi_tl(temp2, const4); + tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); + break; + case OPC2_32_RCRW_INSERT: + temp3 = tcg_temp_new(); + + tcg_gen_movi_tl(temp, width); + tcg_gen_movi_tl(temp2, const4); + tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); + gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); + + tcg_temp_free(temp3); + break; +From encoding point of view d4 is target and not source. +Assumption is here misleading swap of d3 and d4. + + +Detected: +testsuite libstdc++ 9.1.0 delta analysis of Infineon Instruction Set Simulator vs. qemu-system-tricore +fix from 2) is successfull + +Confidence Level for bugfix high. +Is according to spec. and in line with reference Instruction Set Simulator from Infineon. + +Motivation +Reexecution of gcc/g++/libstdc++ testsuites with qemu + +I honor the implementation work which was done by bkoppelmann, vo_lumit@gmx.de |