1 files changed, 76 insertions, 0 deletions
diff --git a/results/classifier/zero-shot/118/architecture-arm/1062 b/results/classifier/zero-shot/118/architecture-arm/1062
new file mode 100644
index 000000000..76cfd385e
--- /dev/null
+++ b/results/classifier/zero-shot/118/architecture-arm/1062
@@ -0,0 +1,76 @@
+architecture: 0.982
+arm: 0.934
+graphic: 0.906
+assembly: 0.851
+device: 0.826
+peripherals: 0.808
+mistranslation: 0.798
+performance: 0.728
+socket: 0.727
+risc-v: 0.676
+register: 0.659
+network: 0.651
+semantic: 0.646
+permissions: 0.635
+ppc: 0.625
+vnc: 0.606
+PID: 0.559
+kernel: 0.537
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+TCG: 0.488
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+debug: 0.476
+i386: 0.414
+VMM: 0.260
+hypervisor: 0.218
+virtual: 0.206
+x86: 0.196
+user-level: 0.178
+KVM: 0.082
+--------------------
+assembly: 0.982
+arm: 0.955
+architecture: 0.818
+register: 0.384
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+ppc: 0.000
+x86: 0.000
+i386: 0.000
+
+AArch64: SCR_EL3.RW behaves incorrectly for CPUs with no AArch32
+Description of problem:
+In the ARM DDI 0487G.a, D13-3572, the SCR_EL3.RW bit is defined as RAO/WI if both EL2 and EL1 don't support Aarch32. However, the function `scr_write` in `target/arm/helper.c` does not reflect this behavior, even though it checks for Aarch32 EL1 support.
+
+This would break this EL3 code, which should run on cpu reset to attempt to return to EL1:
+```asm
+mov x1, #((1<<0)|(1<<2)|(1<<6)|(1<<7)|(1<<8)|(1<<9)) ; EL1h, DAIF masked
+mov SPSR_EL3, x1
+adr x1, 1f
+msr ELR_EL3, x1
+eret
+1:
+; something something
+```
+Additional information:
+