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+Unaligned atomic memory ops support
+Currently x86 instructions translated to the atomic IR ops aren't expecting an alignment.

+Compilers will go out of their way to avoid these unaligned atomics on the x86 side due to the "big ring lock" but they can still be done.

+ARMv8.4-LSE resolves this issue mostly where it relaxes the atomic alignment problem.

+

+But we still need to work with unaligned atomics on older ARMv8 versions, and doesn't resolve the problem of an unaligned atomic crossing a cacheline (x86 works in this instance).

+Will need a backpatch + fallback handling, or if it happens non-frequently, handle it in the signal handler and dispatch a threaded recompiled replacement.
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