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Diffstat (limited to 'results/scraper/launchpad-without-comments/1863685')
| -rw-r--r-- | results/scraper/launchpad-without-comments/1863685 | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/results/scraper/launchpad-without-comments/1863685 b/results/scraper/launchpad-without-comments/1863685 new file mode 100644 index 000000000..49d27a083 --- /dev/null +++ b/results/scraper/launchpad-without-comments/1863685 @@ -0,0 +1,8 @@ +ARM: HCR.TSW traps are not implemented + +On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap data or unified cache maintenance instructions that operate by Set/Way." Quoting the ARM manual: + +If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped to EL2, reported using EC syndrome value 0x18. +If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to EL2, reported using EC syndrome value 0x03. + +However, QEMU does not trap those instructions/registers. This was tested on the branch master of the git repo. \ No newline at end of file |