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id = 1174
title = "aspeed: Fix first byte in I2C old register mode slave receive"
state = "closed"
created_at = "2022-08-25T08:03:29.867Z"
closed_at = "2022-11-14T08:25:19.139Z"
labels = ["Closed::Fixed", "accel: TCG", "workflow::Patch available"]
url = "https://gitlab.com/qemu-project/qemu/-/issues/1174"
host-os = "n/a"
host-arch = "n/a"
qemu-version = "n/a"
guest-os = "Linux"
guest-arch = "arm"
description = """The first byte of data received through the Aspeed I2C slave controller through the old-register mode (specifically byte-buffered, not pool buffered or DMA buffered) is incorrect. It should be the 8-bit I2C slave address for the transfer, which will be the 7-bit I2C slave address of the I2C controller shifted left 1, and 1 or 0 for the lowest bit (is-slave-to-master-transfer, or is-master-to-slave-transfer)."""
reproduce = """You could use the simulated I2C slave EEPROM https://docs.kernel.org/i2c/slave-eeprom-backend.html, but you need another I2C model to send data to it.
Alternatively, you can take this downstream patch and run the qtest in it. It has a test case for slave-mode rx in old-register mode:
https://github.com/facebook/openbmc/blob/helium/common/recipes-devtools/qemu/qemu/0008-hw-misc-Add-byte-by-byte-i2c-network-device.patch"""
additional = """I already created the fix, it's pretty simple, I submitted it to the mailing list and Klaus (the author of that section of the Aspeed I2C controller) reviewed it. https://lore.kernel.org/qemu-devel/20220820225712.713209-1-peter@pjd.dev/#t
This is relatively critical fix, but since slave-mode I2C is not widely used at this point, it's probably fine to ship with this bug. My team uses the master branch for everything anyways."""
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