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Cache Layout wrong on many Zen Arch CPUs
Description of problem:
This is `coreinfo -l` when running Windows as host:
This is `coreinfo -l` when running the same Windows as guest with 6 cores and 6 threads (half of each):
Steps to reproduce:
1. You need a AMD Ryzen 3900X. It has an L3 cache over 3 cores
2. Use `-cpu host,+topoext,host-cache-info=on`
3. Use `coreinfo -l` to see how the L3 cache is distributed
Additional information:
1. When running without `host-cache-info=on` then the L3 cache is spread on all the cpus.
2. `lscpu -e`:
```
CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ
0 0 0 0 0:0:0:0 yes 4672.0698 2200.0000 3800.000
1 0 0 1 1:1:1:0 yes 4672.0698 2200.0000 3800.000
2 0 0 2 2:2:2:0 yes 4672.0698 2200.0000 3800.000
3 0 0 3 4:4:4:1 yes 4672.0698 2200.0000 3800.000
4 0 0 4 5:5:5:1 yes 4672.0698 2200.0000 3800.000
5 0 0 5 6:6:6:1 yes 4672.0698 2200.0000 3800.000
6 0 0 6 8:8:8:2 yes 4672.0698 2200.0000 3800.000
7 0 0 7 9:9:9:2 yes 4672.0698 2200.0000 3610.580
8 0 0 8 10:10:10:2 yes 4672.0698 2200.0000 3800.000
9 0 0 9 12:12:12:3 yes 4672.0698 2200.0000 3800.000
10 0 0 10 13:13:13:3 yes 4672.0698 2200.0000 3800.000
11 0 0 11 14:14:14:3 yes 4672.0698 2200.0000 3800.000
12 0 0 0 0:0:0:0 yes 4672.0698 2200.0000 3800.000
13 0 0 1 1:1:1:0 yes 4672.0698 2200.0000 3800.000
14 0 0 2 2:2:2:0 yes 4672.0698 2200.0000 3800.000
15 0 0 3 4:4:4:1 yes 4672.0698 2200.0000 3800.000
16 0 0 4 5:5:5:1 yes 4672.0698 2200.0000 3800.000
17 0 0 5 6:6:6:1 yes 4672.0698 2200.0000 3800.000
18 0 0 6 8:8:8:2 yes 4672.0698 2200.0000 3800.000
19 0 0 7 9:9:9:2 yes 4672.0698 2200.0000 3800.000
20 0 0 8 10:10:10:2 yes 4672.0698 2200.0000 3800.000
21 0 0 9 12:12:12:3 yes 4672.0698 2200.0000 3800.000
22 0 0 10 13:13:13:3 yes 4672.0698 2200.0000 3800.000
23 0 0 11 14:14:14:3 yes 4672.0698 2200.0000 3800.000
```
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