blob: 3d774638280a737c32af0d7bc38b4cf4366e4c68 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
|
semantic: 0.988
instruction: 0.945
graphic: 0.792
device: 0.739
other: 0.687
assembly: 0.675
vnc: 0.520
network: 0.458
boot: 0.413
socket: 0.407
mistranslation: 0.269
KVM: 0.247
x86 SSE/SSE2/SSE3 instruction semantic bugs with NaN
Description of problem:
The result of SSE/SSE2/SSE3 instructions with NaN is different from the CPU. From Intel manual Volume 1 Appendix D.4.2.2, they defined the behavior of such instructions with NaN. But I think QEMU did not implement this semantic exactly because the byte result is different.
Steps to reproduce:
1. Compile this code
```
void main() {
asm("mov rax, 0x000000007fffffff; push rax; mov rax, 0x00000000ffffffff; push rax; movdqu XMM1, [rsp];");
asm("mov rax, 0x2e711de7aa46af1a; push rax; mov rax, 0x7fffffff7fffffff; push rax; movdqu XMM2, [rsp];");
asm("addsubps xmm1, xmm2");
}
```
2. Execute and compare the result with the CPU. This problem happens with other SSE/SSE2/SSE3 instructions specified in the manual, Volume 1 Appendix D.4.2.2.
- CPU
- xmm1[3] = 0xffffffff
- QEMU
- xmm1[3] = 0x7fffffff
Additional information:
This bug is discovered by research conducted by KAIST SoftSec.
|