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RISC-V: Cannot set SEIP bit of mip csr register in M mode
Description of problem:
Steps to reproduce:
1. run assembly instructions **in M mode**:
```
not t0, x0 // set t0 to 0b11..11
csrs mip, t0 // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values)
csrr t1, mip // read value from mip to t1
```
2. GDB enters the command `display/z $t1` to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set.
3. According to page 47 of [riscv-privileged-20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf), `SEIP is writable in mip`.
4. According to page 81 of the same manual,`If implemented, SEIP is read-only in sip`.
5. However, the above code and results show that the SEIP bit of mip cannot be set by software **in M mode**.
Additional information:
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