summary refs log tree commit diff stats
path: root/results/classifier/zero-shot/118/graphic/2550
blob: fcf8f13f43ac6f9211d1b2660a6c800d725ff478 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
architecture: 0.979
graphic: 0.967
arm: 0.932
boot: 0.931
device: 0.817
register: 0.753
TCG: 0.651
performance: 0.627
files: 0.609
ppc: 0.609
PID: 0.543
semantic: 0.534
kernel: 0.512
vnc: 0.502
assembly: 0.444
user-level: 0.394
peripherals: 0.389
virtual: 0.381
debug: 0.377
VMM: 0.372
socket: 0.371
permissions: 0.317
risc-v: 0.301
network: 0.234
mistranslation: 0.214
hypervisor: 0.143
KVM: 0.120
x86: 0.081
i386: 0.058

GICv3 vGIC system registers not initialized on ARM Cortex-A15
Description of problem:
For Cortex-A15, the GICv3 vGIC registers are not initialized like for AArch64 CPUs, for example Cotex-A35, Cortex-A55, etc
Steps to reproduce:
The setup is not trivial. I can provide a boot image on request. But I hope the problem is straight-forward.
Additional information:
Suggested fix:
```diff
index 20c2737f17..136b513bda 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -569,6 +569,12 @@ static void cortex_a15_initfn(Object *obj)
     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
     cpu->isar.reset_pmcr_el0 = 0x410F3000;
+
+    /* From B3.5 VGIC Type register */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 }

```