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riscv: reset_vec uses CSR even when disabled causing inability to boot
Steps to reproduce:
1. Run any rv32 binary with `./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off`
To view using GDB use `./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off -S -s`
`gdb-multiarch --ex="target remote localhost:1234" -ex "layout asm"`
then type `si` till $pc jumps to zero on `csrr a0, mhartid`
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