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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-02-09 08:50:27 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-02-15 15:53:12 +0100 |
| commit | b8db6be27b2a31ec34640bc7812c4c7b691e71be (patch) | |
| tree | 94108b0ed7eb87f1822a200596d22dc9c15d64e5 | |
| parent | c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c (diff) | |
| download | focaccia-qemu-b8db6be27b2a31ec34640bc7812c4c7b691e71be.tar.gz focaccia-qemu-b8db6be27b2a31ec34640bc7812c4c7b691e71be.zip | |
hw/misc/mips_itu: Remove MIPSITUState::cpu0 field
Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-6-philmd@linaro.org>
| -rw-r--r-- | hw/mips/cps.c | 2 | ||||
| -rw-r--r-- | hw/misc/mips_itu.c | 5 | ||||
| -rw-r--r-- | include/hw/misc/mips_itu.h | 1 |
3 files changed, 0 insertions, 8 deletions
diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 988ceaa0b9..07b73b0a1f 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -103,8 +103,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index d259a88d22..9705efeafe 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -527,10 +527,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) s->num_semaphores); return; } - if (!s->cpu0) { - error_setg(errp, "Missing 'cpu[0]' property"); - return; - } s->cell = g_new(ITCStorageCell, get_num_cells(s)); } @@ -558,7 +554,6 @@ static Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 3a7330ac07..de7400c1fe 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -73,7 +73,6 @@ struct MIPSITUState { /* SAAR */ uint64_t *saar; - ArchCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */ |