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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-05-13 15:28:06 +0000 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-05-13 15:28:06 +0000 |
| commit | dd74ade44d7688f6e1e9a5bf6adb135f740b1317 (patch) | |
| tree | 426bb65bcab3c98dc5a257369abbab77df15be51 | |
| parent | 9de2aa55cdafac5a8f0aa38345d829f086a04cf6 (diff) | |
| download | box64-dd74ade44d7688f6e1e9a5bf6adb135f740b1317.tar.gz box64-dd74ade44d7688f6e1e9a5bf6adb135f740b1317.zip | |
[RV64_DYNAREC] Fixed neg16 SF flag generation
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_emit_math.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_emit_math.c b/src/dynarec/rv64/dynarec_rv64_emit_math.c index f6a7d88b..c076f2d3 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_math.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_math.c @@ -1226,7 +1226,8 @@ void emit_neg16(dynarec_rv64_t* dyn, int ninst, int s1, int s2, int s3) } } IFX(X_SF) { - ANDI(s3, s1, 1 << F_SF); // 1<<F_SF is sign bit, so just mask + SRLI(s3, s1, 15-F_SF); // put sign bit in place + ANDI(s3, s3, 1 << F_SF); // 1<<F_SF is sign bit, so just mask OR(xFlags, xFlags, s3); } IFX(X_PF) { |