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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2023-03-25 00:21:06 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-24 17:21:06 +0100 |
| commit | 5e680e0f6678a9b9c51b603c8ea1333c325b2d26 (patch) | |
| tree | d8b8a246c365ad461be83fa19f96e38666e06a7d /src/include | |
| parent | 45015d6106133b940cbb5f24e08aac4d70bd7de8 (diff) | |
| download | box64-5e680e0f6678a9b9c51b603c8ea1333c325b2d26.tar.gz box64-5e680e0f6678a9b9c51b603c8ea1333c325b2d26.zip | |
[RV64_DYNAREC] Added more opcodes (#633)
* [RV64_DYNAREC] Added 81,83 /2 ADC opcode * [RV64_DYNAREC] Added 34 XOR opcode * [RV64_DYNAREC] Added 66 3B CMP opcode * [RV64_DYNAREC] Added 66 09 OR opcode * [RV64_DYNAREC] Added 66 D1,D3 /5 SHR opcode * [RV64_DYNAREC] Added 30 XOR opcode * [RV64_DYNAREC] Added F6 /5 IMUL opcode * [RV64_DYNAREC] Added 0C OR opcode * [RV64_DYNAREC] Added 2A SUB opcode * [RV64_DYNAREC] Added 66 01 ADD opcode * [RV64_DYNAREC] Added 81,83 /3 SBB opcode * [RV64_DYNAREC] Added 66 69,6B LMUL opcode * [RV64_DYNAREC] Added 66 03 ADD opcode * [RV64_DYNAREC] Added 18 SBB opcode & some fixes & some optims * [RV64_DYNAREC] Added F6 /2 NOT opcode * [RV64_DYNAREC] Added C0 /0 ROL opcode & bug fixes * [RV64_DYNAREC] Added 6A PUSH opcode
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions