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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-04-07 13:31:38 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-04-07 13:31:48 +0200 |
| commit | 02c24dffdc4c802bf1c9dedd180092b17684eae3 (patch) | |
| tree | 2943cfb5b96e956ccf467c8848467a06b5025b79 /src | |
| parent | aa7ee8e65db1e07a875a882b0b43edf5b413152a (diff) | |
| download | box64-02c24dffdc4c802bf1c9dedd180092b17684eae3.tar.gz box64-02c24dffdc4c802bf1c9dedd180092b17684eae3.zip | |
[ARM64_DYNAREC] Fixed, again, FASTROUND=0 for 66 0F E6 opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64/dynarec_arm64_660f.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index c457e760..8461fbcf 100755 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -2233,16 +2233,15 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n MSR_fpsr(x5); ORRw_mask(x4, xZR, 1, 0); //0x80000000 d0 = fpu_get_scratch(dyn); - for(int i=1; i>=0; --i) { + for(int i=0; i<2; ++i) { BFCw(x5, FPSR_IOC, 1); // reset IOC bit MSR_fpsr(x5); if(i) { VMOVeD(d0, 0, v1, i); - FRINTZD(d0, d0); + FCVTZSwD(x1, d0); } else { - FRINTZD(d0, v1); + FCVTZSwD(x1, v1); } - FCVTZSwD(x1, d0); MRS_fpsr(x5); // get back FPSR to check the IOC bit TBZ(x5, FPSR_IOC, 4+4); MOVw_REG(x1, x4); |