[DYNAREC] Added F3 0F 70 opcodes and another fix for F2 0F 70 opcode

2 files changed, 23 insertions, 9 deletions

diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index 6051e319..b51318ef 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -241,7 +241,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("PSHUFLW Gx, Ex, Ib");

             nextop = F8;

             GETEX(v1, 1);

-            GETGX_empty(v0);

+            GETGX(v0);

 

             u8 = F8;

             // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits

@@ -253,14 +253,8 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             MOV64x(x2, u64);

             d0 = fpu_get_scratch(dyn);

             VMOVQDfrom(d0, 0, x2);

-            if(v0!=v1) {

-                VTBL1_8(v0, v1, d0);

-                VMOVeD(v0, 1, v1, 1);

-            } else {

-                VTBL1_8(d0, v1, d0);

-                VMOVeD(v0, 0, d0, 0);

-

-            }

+            VTBL1_8(d0, v1, d0);

+            VMOVeD(v0, 0, d0, 0);

             break;

 

         case 0x7C:

diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index a46f6bad..82dd4964 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -46,6 +46,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     uint8_t nextop, u8;

     uint8_t gd, ed;

     uint8_t wback;

+    uint64_t u64;

     int v0, v1;

     int q0, q1;

     int d0, d1;

@@ -253,6 +254,25 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 VLDR128_U12(v0, ed, fixedaddress);

             }

             break;

+        case 0x70:

+            INST_NAME("PSHUFHW Gx, Ex, Ib");

+            nextop = F8;

+            GETEX(v1, 1);

+            GETGX(v0);

+

+            u8 = F8;

+            // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits

+            u64 = 0;

+            for (int i=0; i<4; ++i) {

+                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+0)<<(i*16+0);

+                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+1)<<(i*16+8);

+            }

+            MOV64x(x2, u64);

+            d0 = fpu_get_scratch(dyn);

+            VMOVQDfrom(d0, 0, x2);

+            VTBL1_8(d0, v1, d0);

+            VMOVeD(v0, 1, d0, 0);

+            break;

 

         case 0x7E:

             INST_NAME("MOVQ Gx, Ex");