[DYNAREC] Added 0F 16/17 opcodes

2 files changed, 43 insertions, 11 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index b90b0bc4..647964e7 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -615,19 +615,25 @@
 #define VSTR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 1, Rn, Dt))
 
 #define LD1R_gen(Q, size, Rn, Rt)           ((Q)<<30 | 0b0011010<<23 | 1<<22 | 0<<21 | 0b110<<13 | (size)<<10 | (Rn)<<5 | (Rt))
-#define VLDQ1R_8(Rt, Rn)                    EMIT(LD1R_gen(1, 0b00, Rn, Rt))
-#define VLDQ1R_16(Rt, Rn)                   EMIT(LD1R_gen(1, 0b01, Rn, Rt))
-#define VLDQ1R_32(Rt, Rn)                   EMIT(LD1R_gen(1, 0b10, Rn, Rt))
-#define VLDQ1R_64(Rt, Rn)                   EMIT(LD1R_gen(1, 0b11, Rn, Rt))
-#define VLD1R_8(Rt, Rn)                     EMIT(LD1R_gen(0, 0b00, Rn, Rt))
-#define VLD1R_16(Rt, Rn)                    EMIT(LD1R_gen(0, 0b01, Rn, Rt))
-#define VLD1R_32(Rt, Rn)                    EMIT(LD1R_gen(0, 0b10, Rn, Rt))
+#define VLDQ1R_8(Vt, Rn)                    EMIT(LD1R_gen(1, 0b00, Rn, Vt))
+#define VLDQ1R_16(Vt, Rn)                   EMIT(LD1R_gen(1, 0b01, Rn, Vt))
+#define VLDQ1R_32(Vt, Rn)                   EMIT(LD1R_gen(1, 0b10, Rn, Vt))
+#define VLDQ1R_64(Vt, Rn)                   EMIT(LD1R_gen(1, 0b11, Rn, Vt))
+#define VLD1R_8(Vt, Rn)                     EMIT(LD1R_gen(0, 0b00, Rn, Vt))
+#define VLD1R_16(Vt, Rn)                    EMIT(LD1R_gen(0, 0b01, Rn, Vt))
+#define VLD1R_32(Vt, Rn)                    EMIT(LD1R_gen(0, 0b10, Rn, Vt))
 
 #define LD1_single(Q, opcode, S, size, Rn, Rt)  ((Q)<<30 | 0b0011010<<23 | 1<<22 | 0<<21 | (opcode)<<13 | (S)<<12 | (size)<<10 | (Rn)<<5 | (Rt))
-#define VLD1_8(Rt, index, Rn)               EMIT(LD1_single(((index)>>3)&1, 0b000, ((index)>>2)&1, (index)&3, Rn, Rt))
-#define VLD1_16(Rt, index, Rn)              EMIT(LD1_single(((index)>>2)&1, 0b010, ((index)>>1)&1, ((index)&1)<<1, Rn, Rt))
-#define VLD1_32(Rt, index, Rn)              EMIT(LD1_single(((index)>>1)&1, 0b100, ((index))&1, 0b00, Rn, Rt))
-#define VLD1_64(Rt, index, Rn)              EMIT(LD1_single(((index))&1, 0b100, 0, 0b01, Rn, Rt))
+#define VLD1_8(Vt, index, Rn)               EMIT(LD1_single(((index)>>3)&1, 0b000, ((index)>>2)&1, (index)&3, Rn, Vt))
+#define VLD1_16(Vt, index, Rn)              EMIT(LD1_single(((index)>>2)&1, 0b010, ((index)>>1)&1, ((index)&1)<<1, Rn, Vt))
+#define VLD1_32(Vt, index, Rn)              EMIT(LD1_single(((index)>>1)&1, 0b100, ((index))&1, 0b00, Rn, Vt))
+#define VLD1_64(Vt, index, Rn)              EMIT(LD1_single(((index))&1, 0b100, 0, 0b01, Rn, Vt))
+
+#define ST1_single(Q, opcode, S, size, Rn, Rt)  ((Q)<<30 | 0b0011010<<23 | 0<<22 | 0<<21 | (opcode)<<13 | (S)<<12 | (size)<<10 | (Rn)<<5 | (Rt))
+#define VST1_8(Vt, index, Rn)               EMIT(ST1_single(((index)>>3)&1, 0b000, ((index)>>2)&1, (index)&3, Rn, Vt))
+#define VST1_16(Vt, index, Rn)              EMIT(ST1_single(((index)>>2)&1, 0b010, ((index)>>1)&1, ((index)&1)<<1, Rn, Vt))
+#define VST1_32(Vt, index, Rn)              EMIT(ST1_single(((index)>>1)&1, 0b100, ((index))&1, 0b00, Rn, Vt))
+#define VST1_64(Vt, index, Rn)              EMIT(ST1_single(((index))&1, 0b100, 0, 0b01, Rn, Vt))
 
 // LOGIC
 #define VLOGIC_gen(Q, opc2, Rm, Rn, Rd)     ((Q)<<30 | 1<<29 | 0b01110<<24 | (opc2)<<22 | 1<<21 | (Rm)<<16 | 0b00011<<11 | 1<<10 | (Rn)<<5 | (Rd))
diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index f17ad3ac..7d3c9afc 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -129,6 +129,32 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             GETGX(v0);

             VZIP2Q_32(v0, v0, q0);

             break;

+        case 0x16:

+            nextop = F8;

+            if((nextop&0xC0)==0xC0) {

+                INST_NAME("MOVLHPS Gx,Ex");

+                GETGX(v0);

+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));

+                VMOVeD(v0, 1, v1, 0);

+            } else {

+                INST_NAME("MOVHPS Gx,Ex");

+                GETGX(v0);

+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);

+                VLD1_64(v0, 1, ed);

+            }

+            break;

+        case 0x17:

+            nextop = F8;

+            INST_NAME("MOVHPS Ex,Gx");

+            GETGX(v0);

+            if(MODREG) {

+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));

+                VMOVeD(v1, 0, v0, 1);

+            } else {

+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);

+                VST1_64(v0, 1, ed);

+            }

+            break;

 

         case 0x1F:

             INST_NAME("NOP (multibyte)");