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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-10-31 02:53:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-30 19:53:04 +0100 |
| commit | 7d1bf95d93d252e44beb0fa74d80d910edc65bda (patch) | |
| tree | 732429097c28195cd878013cde720463e0bb8300 /src | |
| parent | 93cbf59e9e40672b228faf3de77b58917ca0a7e1 (diff) | |
| download | box64-7d1bf95d93d252e44beb0fa74d80d910edc65bda.tar.gz box64-7d1bf95d93d252e44beb0fa74d80d910edc65bda.zip | |
[RV64_DYNAREC] Added more opcodes for vector (#1983)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_0f_vector.c | 21 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_f20f_vector.c | 36 |
2 files changed, 57 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_0f_vector.c b/src/dynarec/rv64/dynarec_rv64_0f_vector.c index 74556ce1..7fd1ccb3 100644 --- a/src/dynarec/rv64/dynarec_rv64_0f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_0f_vector.c @@ -402,6 +402,27 @@ uintptr_t dynarec64_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, GETGX_vector(v0, 1, VECTOR_SEW32); VFMUL_VV(v0, v0, q0, VECTOR_UNMASKED); break; + case 0x5A: + INST_NAME("CVTPS2PD Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + if (MODREG) { + v1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64); + GETGX_empty_vector(v0); + } else { + SMREAD(); + v1 = fpu_get_scratch(dyn); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 1, 0); + LD(x4, ed, fixedaddress); + VMV_S_X(v1, x4); + GETGX_empty_vector(v0); + } + vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 0.5); + d0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + VFWCVT_F_F_V(d0, v1, VECTOR_UNMASKED); + vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 1); + VMV_V_V(v0, d0); + break; case 0x5B: INST_NAME("CVTDQ2PS Gx, Ex"); nextop = F8; diff --git a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c index 8cfe5b5d..2c3352e4 100644 --- a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c @@ -305,6 +305,42 @@ uintptr_t dynarec64_F20F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i } } break; + case 0x5A: + INST_NAME("CVTSD2SS Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + if (MODREG) { + GETGX_vector(v0, 1, VECTOR_SEW64); + v1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64); + } else { + SMREAD(); + v1 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 1, 0); + LD(x4, ed, fixedaddress); + VMV_S_X(v1, x4); + GETGX_vector(v0, 1, VECTOR_SEW64); + } + SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1); + VECTOR_LOAD_VMASK(0b0001, x4, 1); + d0 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + if (v1 & 1 || v0 == v1) { + d1 = fpu_get_scratch_lmul(dyn, VECTOR_LMUL2); + VMV_V_V(d1, v1); + if (rv64_xtheadvector) { + VFNCVT_F_F_W(d0, d1, VECTOR_MASKED); + VMERGE_VVM(v0, v0, d0); // implies VMASK + } else { + VFNCVT_F_F_W(v0, d1, VECTOR_MASKED); + } + } else { + if (rv64_xtheadvector) { + VFNCVT_F_F_W(d0, v1, VECTOR_MASKED); + VMERGE_VVM(v0, v0, d0); // implies VMASK + } else { + VFNCVT_F_F_W(v0, v1, VECTOR_MASKED); + } + } + break; case 0x5C: INST_NAME("SUBSD Gx, Ex"); nextop = F8; |