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| author | ptitSeb <sebastien.chev@gmail.com> | 2025-04-15 14:15:03 +0200 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2025-04-15 14:15:03 +0200 |
| commit | 8f3018e10ce4e77053c839758f8e2bc42b6bfb11 (patch) | |
| tree | 0f9a7450f7a0eb081e6e44d77449a4538b8a8a9d /src | |
| parent | 24b0ba988539ce317d1130c9b9804468426b43c8 (diff) | |
| download | box64-8f3018e10ce4e77053c839758f8e2bc42b6bfb11.tar.gz box64-8f3018e10ce4e77053c839758f8e2bc42b6bfb11.zip | |
[ARM64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and cosim scenario
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c index fb52d141..e8aa70c2 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.c +++ b/src/dynarec/arm64/dynarec_arm64_helper.c @@ -1307,7 +1307,7 @@ static void x87_reflectcache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int if(dyn->n.x87cache[i]!=-1) { ADDw_U12(s3, s2, dyn->n.x87cache[i]); ANDw_mask(s3, s3, 0, 2); // mask=7 // (emu->top + i)&7 - if(neoncache_get_st_f(dyn, ninst, dyn->n.x87cache[i])>=0) { + if(neoncache_get_current_st_f(dyn, dyn->n.x87cache[i])>=0) { int scratch = fpu_get_scratch(dyn, ninst); FCVT_D_S(scratch, dyn->n.x87reg[i]); VSTR64_REG_LSL3(scratch, s1, s3); |