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authorptitSeb <sebastien.chev@gmail.com>2024-02-07 18:01:22 +0100
committerptitSeb <sebastien.chev@gmail.com>2024-02-07 18:02:07 +0100
commita2e01c36bae6d886d2f7115427c818be3fbfbfdb (patch)
treec4631c3d4e3ae6edd01c0e796c0c64984e93ef0f /src
parent774d872f41241251fcd937cca4d7b3e3c07ba954 (diff)
downloadbox64-a2e01c36bae6d886d2f7115427c818be3fbfbfdb.tar.gz
box64-a2e01c36bae6d886d2f7115427c818be3fbfbfdb.zip
[ARM64_DYNAREC] 32bits Shift with 0 amount still wipe upper part of register on 64bits
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_00.c35
1 files changed, 30 insertions, 5 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index 62604eec..5d36f7df 100644
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -1954,7 +1954,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         emit_rol32c(dyn, ninst, rex, ed, u8, x3, x4);
                         WBACK;
                     } else {
-                        FAKEED;
+                        if(MODREG && ! rex.w && !rex.is32bits) {
+                            GETED(1);
+                            MOVw_REG(ed, ed);
+                        } else {
+                            FAKEED;
+                        }
                         F8;
                     }
                     break;
@@ -1968,7 +1973,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         emit_ror32c(dyn, ninst, rex, ed, u8, x3, x4);
                         WBACK;
                     } else {
-                        FAKEED;
+                        if(MODREG && ! rex.w && !rex.is32bits) {
+                            GETED(1);
+                            MOVw_REG(ed, ed);
+                        } else {
+                            FAKEED;
+                        }
                         F8;
                     }
                     break;
@@ -2015,7 +2025,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
                         WBACK;
                     } else {
-                        FAKEED;
+                        if(MODREG && ! rex.w && !rex.is32bits) {
+                            GETED(1);
+                            MOVw_REG(ed, ed);
+                        } else {
+                            FAKEED;
+                        }
                         F8;
                     }
                     break;
@@ -2029,7 +2044,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         emit_shr32c(dyn, ninst, rex, ed, u8, x3, x4);
                         WBACK;
                     } else {
-                        FAKEED;
+                        if(MODREG && ! rex.w && !rex.is32bits) {
+                            GETED(1);
+                            MOVw_REG(ed, ed);
+                        } else {
+                            FAKEED;
+                        }
                         F8;
                     }
                     break;
@@ -2043,7 +2063,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         emit_sar32c(dyn, ninst, rex, ed, u8, x3, x4);
                         WBACK;
                     } else {
-                        FAKEED;
+                        if(MODREG && ! rex.w && !rex.is32bits) {
+                            GETED(1);
+                            MOVw_REG(ed, ed);
+                        } else {
+                            FAKEED;
+                        }
                         F8;
                     }
                     break;