[DYNAREC] Added 66 0F 6B

2 files changed, 39 insertions, 1 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index e7feabec..a97b4a8f 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -1081,4 +1081,31 @@
 #define VTRNQ2_16(Vd, Vn, Vm)       EMIT(TRN_gen(1, 0b01, Vm, 1, Vn, Vd))
 #define VTRNQ2_8(Vd, Vn, Vm)        EMIT(TRN_gen(1, 0b00, Vm, 1, Vn, Vd))
 
+// QXTN / QXTN2
+#define QXTN_vector(Q, U, size, Rn, Rd)     ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b10100<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 64->32 with Signed saturation and fit lower part of Rd
+#define SQXTN_32(Rd, Rn)            EMIT(QXTN_vector(0, 0, 0b10, Rn, Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 64->32 with Signed saturation and fit higher part of Rd
+#define SQXTN2_32(Rd, Rn)           EMIT(QXTN_vector(1, 0, 0b10, Rn, Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 32->16 with Signed saturation and fit lower part of Rd
+#define SQXTN_16(Rd, Rn)            EMIT(QXTN_vector(0, 0, 0b01, Rn, Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 32->16 with Signed saturation and fit higher part of Rd
+#define SQXTN2_16(Rd, Rn)           EMIT(QXTN_vector(1, 0, 0b01, Rn, Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 16->8 with Signed saturation and fit lower part of Rd
+#define SQXTN_8(Rd, Rn)             EMIT(QXTN_vector(0, 0, 0b00, Rn, Rd))
+// Signed saturating extract Narrow, takes Rn element and reduce 16->8 with Signed saturation and fit higher part of Rd
+#define SQXTN2_8(Rd, Rn)            EMIT(QXTN_vector(1, 0, 0b00, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 64->32 with Unsigned saturation and fit lower part of Rd
+#define SQXTUN_32(Rd, Rn)           EMIT(QXTN_vector(0, 1, 0b10, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 64->32 with Unsigned saturation and fit higher part of Rd
+#define SQXTUN2_32(Rd, Rn)          EMIT(QXTN_vector(1, 1, 0b10, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 32->16 with Unsigned saturation and fit lower part of Rd
+#define SQXTUN_16(Rd, Rn)           EMIT(QXTN_vector(0, 1, 0b01, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 32->16 with Unsigned saturation and fit higher part of Rd
+#define SQXTUN2_16(Rd, Rn)          EMIT(QXTN_vector(1, 1, 0b01, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 16->8 with Unsigned saturation and fit lower part of Rd
+#define SQXTUN_8(Rd, Rn)            EMIT(QXTN_vector(0, 1, 0b00, Rn, Rd))
+// Signed saturating extract Unsigned Narrow, takes Rn element and reduce 16->8 with Unsigned saturation and fit higher part of Rd
+#define SQXTUN2_8(Rd, Rn)           EMIT(QXTN_vector(1, 1, 0b00, Rn, Rd))
+
 #endif  //__ARM64_EMITTER_H__
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 4a0a1e6b..23000db5 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -250,7 +250,18 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             GETEX(q1, 1);

             VZIP2Q_32(q0, q0, q1);

             break;

-

+        case 0x6B:

+            INST_NAME("PACKSSDW Gx,Ex");

+            nextop = F8;

+            GETGX(v0);

+            GETEX(v1, 0);

+            SQXTN_16(v0, v0);

+            if(v0==v1) {

+                VMOVeD(v0, 1, v0, 0);

+            } else {

+                SQXTN2_16(v0, v1);

+            }

+            break;

         case 0x6C:

             INST_NAME("PUNPCKLQDQ Gx,Ex");

             nextop = F8;