[DYNAREC] Added 66 0F 5B opcode

2 files changed, 10 insertions, 2 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 0d5bc7ff..e7feabec 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -949,7 +949,7 @@
 #define VFCVTMUQS(Vd, Vn)           EMIT(FCVT_vector(1, 1, 0, 0, 1, Vn, Vd))
 #define VFCVTMUQD(Vd, Vn)           EMIT(FCVT_vector(1, 1, 0, 1, 1, Vn, Vd))
 
-#define FCVT2_vector(Q, U, o2, sz, o1, Rn, Rd)       ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o2)<<23 | (sz)<<22) | 0b10000<<17 | 0b1101<<13 | (o1)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define FCVT2_vector(Q, U, o2, sz, o1, Rn, Rd)       ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o2)<<23 | (sz)<<22 | 0b10000<<17 | 0b1101<<13 | (o1)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Floating-point Convert to (Un)signed integer, rounding to nearest with ties to even
 #define VFCVTNSS(Vd, Vn)            EMIT(FCVT2_vector(0, 0, 0, 0, 0, Vn, Vd))
 #define VFCVTNSD(Vd, Vn)            EMIT(FCVT2_vector(0, 0, 0, 1, 0, Vn, Vd))
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 7837bfa6..4a0a1e6b 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -194,10 +194,18 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x5A:

             INST_NAME("CVTPD2PS Gx, Ex");

             nextop = F8;

-            GETGX_empty(v0);

             GETEX(v1, 0);

+            GETGX_empty(v0);

             FCVTXN(v0, v1);

             break;

+        case 0x5B:

+            INST_NAME("CVTPS2DQ Gx, Ex");

+            nextop = F8;

+            GETEX(v1, 0);

+            GETGX_empty(v0);

+            // need rounding? using "toward 0 for now"

+            VFCVTZSQS(v0, v1);

+            break;

 

         case 0x60:

             INST_NAME("PUNPCKLBW Gx,Ex");