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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2024-11-02 02:36:23 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-01 19:36:23 +0100 |
| commit | cf9f8d05351ec617038e4a612a145a3a28c01309 (patch) | |
| tree | d4f107f721e7766d88ad2a9448d058566c703058 /src | |
| parent | 9e43737e1823ee49649307c799df98a910ae236e (diff) | |
| download | box64-cf9f8d05351ec617038e4a612a145a3a28c01309.tar.gz box64-cf9f8d05351ec617038e4a612a145a3a28c01309.zip | |
[RV64_DYNAREC] Added more opcodes for vector (#1992)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_660f_vector.c | 1 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_f30f_vector.c | 38 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c index b916bc39..e47a8a77 100644 --- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c @@ -850,6 +850,7 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i VECTOR_LOAD_VMASK((u8 & 0xf), x4, 1); VMERGE_VVM(q0, v1, d0); break; + case 0x63: return 0; default: DEFAULT_VECTOR; } break; diff --git a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c index ac580845..0081552d 100644 --- a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c @@ -96,6 +96,44 @@ uintptr_t dynarec64_F30F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i SMWRITE2(); } break; + case 0x12: + INST_NAME("MOVSLDUP Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + if (MODREG) { + q1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64); + } else { + SMREAD(); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0); + q1 = fpu_get_scratch(dyn); + VLE32_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1); + } + GETGX_empty_vector(q0); + ADDI(x4, xZR, 32); + v0 = fpu_get_scratch(dyn); + VSLL_VX(q0, q1, x4, VECTOR_UNMASKED); + VSRL_VX(v0, q0, x4, VECTOR_UNMASKED); + VOR_VV(q0, q0, v0, VECTOR_UNMASKED); + break; + case 0x16: + INST_NAME("MOVSHDUP Gx, Ex"); + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + if (MODREG) { + q1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64); + } else { + SMREAD(); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0); + q1 = fpu_get_scratch(dyn); + VLE32_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1); + } + GETGX_empty_vector(q0); + ADDI(x4, xZR, 32); + v0 = fpu_get_scratch(dyn); + VSRL_VX(q0, q1, x4, VECTOR_UNMASKED); + VSLL_VX(v0, q0, x4, VECTOR_UNMASKED); + VOR_VV(q0, q0, v0, VECTOR_UNMASKED); + break; case 0x1E: return 0; case 0x2A: |