[DYNAREC] Added F3 0F 52 opcode

2 files changed, 31 insertions, 0 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index ef849bf4..f8aa400a 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -794,6 +794,15 @@
 #define FMOVS(Sd, Sn)                       EMIT(FMOV_register(0b00, Sn, Sd))
 #define FMOVD(Dd, Dn)                       EMIT(FMOV_register(0b01, Dn, Dd))
 
+#define FMOV_vector_imm(Q, op, abc, defgh, Rd)  ((Q)<<30 | (op)<<29 | 0b0111100000<<19 | (abc)<<16 | 0b1111<<12 | 1<<10 | (defgh)<<5 | (Rd))
+#define VFMOVS_8(Vd, u8)                    EMIT(FMOV_vector_imm(0, 0, ((u8)>>5)&0b111, (u8)&0b11111, Vd))
+#define VFMOVSQ_8(Vd, u8)                   EMIT(FMOV_vector_imm(1, 0, ((u8)>>5)&0b111, (u8)&0b11111, Vd))
+#define VFMOVDQ_8(Vd, u8)                   EMIT(FMOV_vector_imm(1, 1, ((u8)>>5)&0b111, (u8)&0b11111, Vd))
+
+#define FMOV_scalar_imm(type, imm8, Rd)     (0b11110<<24 | (type)<<22 | 1<<21 | (imm8)<<13 | 0b100<<10 | (Rd))
+#define FMOVS_8(Sd, u8)                     EMIT(FMOV_scalar_imm(0b00, u8, Sd))
+#define FMOVD_8(Dd, u8)                     EMIT(FMOV_scalar_imm(0b01, u8, Dd))
+
 // VMOV
 #define VMOV_element(imm5, imm4, Rn, Rd)    (1<<30 | 1<<29 | 0b01110000<<21 | (imm5)<<16 | (imm4)<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VMOVeB(Vd, i1, Vn, i2)              EMIT(VMOV_element(((i1)<<1) | 1, (i2), Vn, Vd))
@@ -1083,6 +1092,12 @@
 #define SCVTQFS(Vd, Vn)             EMIT(SCVTF_vector(1, 0, 0, Vn, Vd))
 #define SCVTQFD(Vd, Vn)             EMIT(SCVTF_vector(1, 0, 1, Vn, Vd))
 
+// FRINTI Floating-point Round to Integral, using current rounding mode from FPCR (vector).
+#define FRINT_vector(Q, U, o2, sz, o1, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o2)<<23 | (sz)<<22 | 0b10000<<17 | 0b1100<<13 | (o1)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRINTIS(Vd,Vn)             EMIT(FRINT_vector(0, 1, 1, 0, 1, Vn, Vd))
+#define VFRINTISQ(Vd,Vn)            EMIT(FRINT_vector(1, 1, 1, 0, 1, Vn, Vd))
+#define VFRINTIDQ(Vd,Vn)            EMIT(FRINT_vector(1, 1, 1, 1, 1, Vn, Vd))
+
 // FMAX / FMIN
 #define FMINMAX_vector(Q, U, o1, sz, Rm, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o1)<<23 | (sz)<<22 | 0b1<<21 | (Rm)<<16 | 0b11110<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFMINS(Vd, Vn, Vm)          EMIT(FMINMAX_vector(0, 0, 1, 0, Vm, Vn, Vd))
diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index 6b395fe2..d297effc 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -173,6 +173,22 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             FSQRTS(d1, d0);

             VMOVeS(v0, 0, d1, 0);

             break;

+        case 0x52:

+            INST_NAME("RSQRTSS Gx, Ex");

+            nextop = F8;

+            GETGX(v0);

+            GETEX(v1, 0);

+            d0 = fpu_get_scratch(dyn);

+            // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000

+            // and want 1.0f = 0x3f800000

+            // so 00111111 10000000 00000000 00000000

+            // a = 0, b = 1, c = 1, d = 1, efgh=0

+            // 0b01110000

+            FMOVS_8(d0, 0b01110000);

+            FSQRTS(v0, v1);

+            FDIVS(d0, d0, v0);

+            VMOVeS(v0, 0, d0, 0);

+            break;

 

         case 0x58:

             INST_NAME("ADDSS Gx, Ex");