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| author | ptitSeb <sebastien.chev@gmail.com> | 2025-03-08 20:58:04 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2025-03-08 20:58:04 +0100 |
| commit | e8a7bef5a072b21c4e62ae3874aec51b95e9f6b9 (patch) | |
| tree | eeeda136222494500a724a6503d83c74889e05f0 /src | |
| parent | c2f73e6de014c89c23e6373585d785f3ae4b72b2 (diff) | |
| download | box64-e8a7bef5a072b21c4e62ae3874aec51b95e9f6b9.tar.gz box64-e8a7bef5a072b21c4e62ae3874aec51b95e9f6b9.zip | |
[ARM64_DYNAREC] Fixed a potential issue with AVX.0F 50 opcode
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_avx_0f.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_avx_0f.c b/src/dynarec/arm64/dynarec_arm64_avx_0f.c index 387faf1b..79b9988f 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_avx_0f.c @@ -302,7 +302,7 @@ uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int // EX is an xmm reg q0 = fpu_get_scratch(dyn, ninst); for(int l=0; l<1+vex.l; ++l) { - if(!l) { GETEX(v0, 0, 0); } else { GETEY(v0); } + if(!l) { GETEX_Y(v0, 0, 0); } else { GETEY(v0); } SQXTN_16(q0, v0); // reduces the 4 32bits to 4 16bits VMOVQDto(x1, q0, 0); LSRx(x1, x1, 15); |