diff options
| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-23 11:03:55 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-23 11:03:55 +0100 |
| commit | ed452e81ae59982da75774ad52f6bfafe24096fb (patch) | |
| tree | ff9067ce3166253b3b90169c6839a56652123f68 /src | |
| parent | 604da55f0821a5272bd24a5cfae1d95abfc00839 (diff) | |
| download | box64-ed452e81ae59982da75774ad52f6bfafe24096fb.tar.gz box64-ed452e81ae59982da75774ad52f6bfafe24096fb.zip | |
[DYNAREC] Improved CMPLESS accuracy
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_f30f.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index 24cb0e67..3ff24d0a 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -209,11 +209,11 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n } else { FCMPS(v0, v1); } - MOV32w(x2, 0); switch(u8&7) { case 0: CSETMw(x2, cEQ); break; // Equal case 1: CSETMw(x2, cMI); break; // Less than - case 2: CSETMw(x2, cLE); break; // Less or equal + case 2: //CSETMw(x2, cLE); break; // Less or equal (or unordered on ARM64, not on x86...) + CSETMw(x2, cPL); CSINVw(x2, xZR, x2, cEQ); break; // so use a 2 step here, but 1st test inverted because 2nd step invert again case 3: CSETMw(x2, cVS); break; // NaN case 4: CSETMw(x2, cNE); break; // Not Equal (or unordered on ARM, not on X86...) case 5: CSETMw(x2, cCS); break; // Greater or equal or unordered |